Tutorial 1 (10:00–13:00, November 22)
Testing and Monitoring of Die-to-Die Interconnects in a 2.5D/3D IC
Speaker: Prof. Shi-Yu Huang (National Tsing Hua University)
Abstract: For years, boundary scan test has been the predominant standard for chip-to-chip interconnect test, which targets mainly catastrophic stuck-at faults and hard bridging faults. However, this standard is now facing severe challenge. Amid the evolution of die-level integration into the era of interposer- or InFO-based 2.5-D ICs and/or TSV-based 3D stacked ICs, die-to-die interconnects could operate in a very high speed, with an end-to-end delay of only a few hundreds of picoseconds. Parametric defects (like small delay faults, resistive open/bridging faults, leakage faults, etc) have been identified as potential threats to the yield and reliability of a 2.5D/3D IC product. Fortunately, researchers have quickly reacted to this challenge by developing many practical and effective test methods.
These new developments will have a far-reaching effect, as they quietly changing the landscape of 2.5D/3D IC test. System architects, test engineers, and product engineers will need to consider these new test options as they ponder over various test schemes in dealing with parametric faults in pre-bond test and post-bond test, online monitoring scheme, and potential yield and reliability enhancement schemes such as Built-In Self-Repair (BISR) so as to ensure the overall quality of the die-to-die interconnects in a 2.5D/3D IC product.
Biography: Shi-Yu Huang is an IEEE senior member. He received his B.S. and M.S. degrees in Electrical Engineering from National Taiwan University in 1988 and 1992, respectively, and his Ph.D. degree in Electrical and Computer Engineering from University of California, Santa Barbara, in 1997. He joined the faculty of the Electrical Engineering Department, National Tsing Hua University, Taiwan, in 1999. More recently, his research is concentrated on all-digital timing circuit designs, such as all-digital phase-locked loop (PLL), all-digital delay-locked loop (DLL), time-to-digital converter (TDC), and their applications to parametric fault testing and reliability enhancement for 3D-ICs. He has published more than 160 refereed technical papers (including 60 journal papers). Dr. Huang ever co-founded a company in 2007-2012, TinnoTek Inc., specializing a cell-based PLL compiler and system-level power estimation tools. He is a co-receipient of the best-paper awards for several times from IEEE technical events (VLSI-DAT’2006, VLSI-DAT’2013, ATS’2014, WRTLT’2017, ISOCC’2018, respectively).
Tutorial 2 (14:00–17:00, November 22)
Automotive Safety, Reliability, and Test Solutions
Speakers: Dr. Riccardo Mariani (NVIDIA) and Dr. Yervant Zorian (Synopsys)
Abstract: Given today’s fast-growing automotive semiconductor industry, this tutorial will discuss the implications of automotive quality, functional safety, and reliability on all aspects of automotive SOC lifecycle, while accelerating time to market for these semiconductor ICs. The automotive SOC lifecycle stages will include design, silicon bring-up, volume production, and particularly in-system operation. Today’s automotive safety critical chips need multiple in-system modes, such as power-on and power-off self-test and repair (key-on/key-off), periodic in-field self-test during mission mode, advanced error correction solutions, etc. This tutorial will analyze these specific in-system test modes and the discuss the benefits of using ISO 26262 including its second edition, and several newer standardization efforts, in order to ensure that standardized functional safety requirements are met.
Biography (Dr. Riccardo Mariani): Riccardo Mariani is widely recognized as an expert in functional safety and integrated circuit reliability. In his current role as VP of Industry Safety at NVIDIA, he is responsible for driving safety alignment across NVIDIA’s automotive and embedded business units. To this end, he is responsible for developing cohesive safety strategies and cross-segment safety processes, architecture, and products that can be leveraged across NVIDIA’s AI-based hardware and software platforms. Prior to NVIDIA, he was chief functional safety technologist at Intel Corporation, where he oversaw strategies and technologies for IoT applications that require functional safety, high reliability and performance, such as autonomous driving, transportation and industrial systems. Riccardo Mariani is the current VP of IEEE Computer Society Standardisation Activities and also chair of the IEEE Computer Society Functional Safety Standards Committee (FSSC). Mariani spent the bulk of his career as CTO of Yogitech, an industry leader in functional safety technologies. Before co-founding the Italian company in 2000, he was technical director at Aurelia Microelettronica, where his responsibilities included leading high-reliability topics in projects with CERN in Geneva. A prolific author and respected inventor in the functional safety field, Mariani has contributed to multiple industry standards efforts throughout his career, including leading the ISO 26262-11 part specific to semiconductors. He has also won the SGS-Thomson Award and the Enrico Denoth Award for his engineering achievements. He holds a bachelor’s degree in electronic engineering and a Ph.D. in microelectronics from the University of Pisa in Italy.
Biography (Dr. Yervant Zorian): Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia’s National Medal of Science.
He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.